Chip array structure for laser diodes and packaging device for the same

ABSTRACT

A chip array structure for laser diodes, formed on an active surface of a semiconductor chip produced from a semiconductor process includes a plurality of light-emitting elements in an array arrangement, at least one insulation wall, at least two wire bond areas and a plurality of connection electrodes. The insulation wall separates the light-emitting elements into at least two light-emitting districts. The wire bond areas are positioned respective to the corresponding light-emitting districts. The connection electrodes electrically couple the wire bond areas with the corresponding light-emitting districts. The wire bond areas have independent electrodes, and the light-emitting districts are electrically isolated by the insulation wall.

BACKGROUND OF INVENTION

1. Field of the Invention

The invention relates to a chip array structure for laser diodes, andmore particularly to the chip array structure on the same semiconductorchip that includes at least one insulation wall to separate plurallight-emitting elements originally in an array arrangement into a numberof isolated light-emitting districts. In this invention, each of thelight-emitting districts is corresponding to an individual wire bondarea (welding pad) so as to achieve a homogeneous illumination effect bymixing lights from different light-emitting districts. Also, theillumination pattern of the laser diode can be further adjusted byappropriate current controls.

2. Description of the Prior Art

Recently in the art, light-communication technology has become one ofthe mainstream frames for constructing advanced networking. It isalready feasible in the future that data transmission can be completelyfulfilled by a light-based network. To enhance performance of the lighttransmission, various semiconductor laser devices have become thedevoted topics for the related manufacturers and researchers in the art.Plenty of those laser devices already in the market place include thevertical cavity surface emitting Laser (VCSEL), the horizontal cavitysurface emitting Laser (HCSEL), the resonant cavity light emitting diode(RCLED) and so on.

Referring to FIG. 1, a top view of a conventional laser diode array chipis schematically shown. In the laser diode array chip 9, plural laserdiodes 92 are mounted to the same semiconductor chip 91 in an arrayarrangement by a semiconductor manufacturing process. A bonding pad 93located at a lateral side of the array of the laser diodes 92 iselectrically connected with each of the laser diodes 92 through aconnection electrode 94. In the art, the single bonding pad 93constructs the common wire bond area for all the laser diodes 92. Evenin an alternative design not shown herein, these laser diodes 92 areelectrically integrated through bifurcated bonding pads from the samewire bond area. In those conventional designs, currents distributed tothe laser diodes 92 on the single bonding pad 93 or the common wire bondcannot be comfortably equalized. In particular, the current decayingrate as well as the electric stability might be significantly variedbetween the near-side diodes 92 and the far-side diodes 92 with respectto the same bonding pad 93. Thereby, the shortcoming of uneven lightpowers and performances is inevitable. In addition, for all the laserdiodes 92 are mounted on the same bonding pad 93, an equivalent resonanteffect can be induced so as to add comprehensive coherence to photosfrom various laser diodes 92. Thereupon, the conventional laser diodearray chip 9 is highly possible to present a donut-type illuminationpattern, which may make no difference with the illumination pattern of asingle laser diode 92. Apparently, the merits from using plural diodes92 are vanished.

Particularly, a single semiconductor laser chip to have a big number oflaser elements (for example, an 8×8 array to have 64 elements, or a16×16 array to have 256 elements) is now normal to current designs. Asthe conventional laser chip is packaged into a light-emitting module,the wire-bond process is usually applied to mount the laser chip ontothe substrate of the light-emitting module by gold-wiring the bondingpad of the laser chip to a single electrode area or an electrode stem ofthe substrate. However, due to the features of high-correlatedillumination patterns in the conventional laser chip design, and also tothe increased instability in power supply with respect to an increasednumber of laser elements in a single laser chip, the uneven currentflows would inevitably cause an inhomogeneous illumination problem tothose laser elements. Obviously, such a performance in the laser chip isfar from satisfaction, and thus a comprehensive improvement isdefinitely needed and urgent.

SUMMARY OF THE INVENTION

Accordingly, it is the primary object of the present invention toprovide a chip array structure for laser diodes, in which at least aninsulation wall is introduced to separate plural arrayed light-emittingelements into a number of isolated light-emitting districts that areindividually energized, such that the problems of uneven powerdistribution and donut-type illumination pattern can be substantiallyimproved.

It is a secondary object of the present invention to provide a chiparray structure for laser diodes, in which the illumination pattern canbe adjusted by appropriate current controls upon differentlight-emitting districts.

In the present invention, the chip array structure for laser diodes,formed on an active surface of a semiconductor chip produced by asemiconductor process, includes a plurality of light-emitting elementsin an array arrangement, at least one insulation wall, at least two wirebond areas and a plurality of connection electrodes. In the presentinvention, the light-emitting elements can be the vertical cavitysurface emitting Lasers (VCSEL), the horizontal cavity surface emittingLasers (HCSEL), or the resonant cavity light emitting diodes (RCLED).

The aforesaid at least one insulation wall located on the active surfaceof the concerned semiconductor chip is to separate the light-emittingelements into at least two light-emitting districts. The wire bond areasare located on the active surface at positions respective to thecorresponding light-emitting districts. The connection electrodes are toelectrically couple the wire bond areas with the correspondinglight-emitting districts. The polarity of a bottom surface of thesemiconductor chip is different to that of the wire bond areas, but thepolarities of the wire bond areas are the same, though the wire bondareas are isolated from each other and can be independently powered byan identical external power source.

The light-emitting districts are isolated without any electriccommunication by the at least one insulation wall. In the presentinvention, different electric currents can be sent to individuallight-emitting district for a purpose of illumination adjustmentthereupon.

In addition, the aforesaid uneven power distribution problem on thesingle bonding pad can be lessened by appropriately adjusting the numberand the arrangement of light-emitting elements in individuallight-emitting district. Thereby, the illumination pattern of the chipcan be adjusted by predetermining the illuminations of individuallight-emitting districts.

All these objects are achieved by the chip array structure for laserdiodes described below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be specified with reference to itspreferred embodiment illustrated in the drawings, in which:

FIG. 1 is a schematic top view of a conventional chip array structurefor laser diodes;

FIG. 2 is a schematic top view of a first embodiment of the chip arraystructure for laser diodes in accordance with the present invention;

FIG. 3 is a schematic top view of a second embodiment of the chip arraystructure for laser diodes in accordance with the present invention;

FIG. 4 is a schematic top view of a third embodiment of the chip arraystructure for laser diodes in accordance with the present invention;

FIG. 5 is a schematic top view of a fourth embodiment of the chip arraystructure for laser diodes in accordance with the present invention; and

FIG. 6 is a schematic top view of a preferred packaging device for thechip array structure for laser diodes in accordance with the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention disclosed herein is directed to a chip array structure forlaser diodes and a packaging device for the chip array structure. In thefollowing description, numerous details are set forth in order toprovide a thorough understanding of the present invention. It will beappreciated by one skilled in the art that variations of these specificdetails are possible while still achieving the results of the presentinvention. In other instance, well-known components are not described indetail in order not to unnecessarily obscure the present invention.

Referring now to FIG. 2, a first embodiment of the chip array structurefor laser diodes in accordance with the present invention isschematically shown in a top view. In this first embodiment, the chiparray structure 1 is formed on an active surface 111 of a semiconductorchip 11 produced from a semiconductor cutting process and includes aplurality of light-emitting elements 12, at least one insulation wall13, at least two wire bond areas 14 and a plurality of connectionelectrodes 16. As shown, the first embodiment 1 is a 8×8 chip arraystructure having 64 light emitting elements 12, in which, for anexplanatory purpose, an X/Y coordinate system is defined to locate eachof the light-emitting elements 12 at the corresponding integral node(x,y).

In the present invention, the chip array structure for laser diodes 1can be a multi-layer cladding structure cut from a III˜V semiconductorwafer who has a plurality of semiconductor chips 11 thereon before thesemiconductor cutting process. Every of the isolated semiconductor chips11 is identically structured to have the aforesaid plurality oflight-emitting elements 12, the at least one insulation wall 13, the atleast two wire bond areas 14 and the plurality of connection electrodes16. For the cladding technique of wafers and the semiconductor processare not the concerned of the present invention, the related detailsthereabout would be omitted herein.

The semiconductor chip 11 has two opposing surfaces, the active surface111 and a bottom surface 112. A metal electrode layer is formed on thebottom surface 112, and the polarity (N or P) of the metal electrodelayer is opposite to that of the wire bond areas 14 on the activesurface 11. In the first embodiment, the wire bond areas 14 are all Pwelding pads, while the bottom surface 112 is an N electrode.

In the first embodiment as shown in FIG. 2, the light-emitting elements12 include 64 elements formed in an 8×8 square array on the activesurface 111 of the semiconductor chip 11. The wire bond areas 14 (fiveshown in this embodiment) are to surround laterally the square array. Inanother embodiment of the present invention (not shown here), thelight-emitting elements 12 can also include 256 elements formed in a16×16 array. In the present invention, the light-emitting element 12 canbe one of the vertical cavity surface emitting Laser (VCSEL), thehorizontal cavity surface emitting Laser (HCSEL), the resonant cavitylight emitting diode (RCLED), and any light-emitting element the like.

The insulation wall 13 constructed on the semiconductor chip 11 is toseparate, in an isolated manner, the light-emitting elements 12 into atleast two light-emitting districts 15. On the active surface 111, eachof the light-emitting districts 15 is electrically isolated from eachother and may include an individual amount of the light-emittingelements 12. In the present invention, different currents can be sent todifferent light-emitting districts 15, and various currents can beoptionally sent into a single light-emitting district 15. Withappropriate current controls on the light-emitting districts 15 as wellas on a particular single light-emitting district 15, illumination ofthe chip array structure 1 can thus be adjusted. In addition, the amountand/or the arrangement of the light-emitting elements 12 in eachlight-emitting district 15 can also be adjusted to achieve any ofvarious illumination patterns. Upon controls of the currents into thelight-emitting districts 15, the amount of the light-emitting elements12 in each the light-emitting district 15, and the arrangement thereof,the aforesaid coherence of photos from the light-emitting districts 15can be thus broken, and thereby various illumination patterns can befeasible; such that the aforesaid donut-type illumination patterninduced from the laser resonant effect can be avoided. In the firstembodiment, at least one insulation wall 13 is introduced to divide thelight-emitting elements 12 into five light-emitting districts 15I˜15V onthe semiconductor chip 11, as shown in FIG. 2. Also, five connectionelectrodes 16 are applied to connect electrically, in an independentway, the five light-emitting districts 15I˜15V to the corresponding wirebond areas 14I˜14V.

In the present invention, the wire bond areas 14I˜14V are formed byindividual conductive metal bonding pads and located at predeterminedpositions on the active surface 111 of the semiconductor chip 11. Eachof the wire bond areas 14I˜14V is accounted and electrically connectedto a corresponding one of the light-emitting districts 15I˜15V, and ispolar-independent (P-electrode for example). Namely, the polaritys ofthe wire bond area 14 and the corresponding light-emitting district 15connected in between by the connection electrode 16 are identical. Byproviding the insulation wall 13 to separate electrically thelight-emitting districts 15I˜15V, each of the light-emitting districts15I˜15V is electrically related only to the corresponding one of thewire bond areas 14I˜14V, such that the control of the light-emittingelements 12 within a specific light-emitting district 15 by inputting aspecific current to the concerned light-emitting district 15 through thecorresponding wire bond area 14 can be achieved.

Further, for the amounts, the arrangements and the input currents of thelight-emitting elements 12 in individual light-emitting districts15I˜15V might be various, the illumination and the pattern of a specificor more light-emitting districts 15I˜15V can be arbitrarily adjusted soas to obtain a whole homogeneous illumination and also a satisfactoryillumination pattern of the chip array structure 1. In addition, thepoor illumination performance from the ill distribution of inputcurrents to the light-emitting elements 12 and the unacceptabledonut-type illumination pattern from the strong photo coherence inducedby the laser resonance on the conventional unique wire bond area(welding pad) can thus be substantially avoided.

Accordingly, referred to FIG. 2, each of the individual light-emittingdistricts 15I˜15V of the first embodiment of the chip array structure 1for laser diodes in accordance with the present invention can be definedby ranges of corresponding coordinates (x, y) in the X/Y coordinatesystem as follows.

Light-emitting district 15I: (3˜6, 3˜6);

Light-emitting district 15II: (1˜2, 1˜4), (3˜4, 1˜2);

Light-emitting district 15III: (1˜2, 5˜8), (3˜4, 7˜8);

Light-emitting district 15IV: (5˜8, 7˜8), (7˜8, 5˜6); and

Light-emitting district 15V: (5˜8, 1˜2), (7˜8, 3˜4).

From the (x, y) definitions in FIG. 2, the light-emitting district 15Iis surrounded by the other four corner light-emitting districts15II˜15V. Also, each of the light-emitting districts 15I˜15V iselectrically and independently connected to a corresponding one of theisolated wire bond areas 14I˜14V via the respective connectionelectrodes 16. As shown, the locations of the wire bond areas 14I˜14Vwith respect to the array of the light-emitting elements 12 are definedas follows.

The wire bond area 14I for the light-emitting district 15I is locatedlower to (in FIG. 2) the array of the light-emitting elements 12;

The wire bond area 14II for the light-emitting district 15II is locatedleft to (in FIG. 2) the array of the light-emitting elements 12;

The wire bond area 14III for the light-emitting district 15III islocated upper and left to (in FIG. 2) the array of the light-emittingelements 12;

The wire bond area 14IV for the light-emitting district 15IV is locatedupper and right to (in FIG. 2) the array of the light-emitting elements12; and

The wire bond area 14V for the light-emitting district 15V is locatedright to (in FIG. 2) the array of the light-emitting elements 12.

For example, in the first embodiment, for different currents can beindividually provided to the wire bond areas 14I˜14V through thecorresponding connection electrodes 16, different illuminationperformances can thus be present to the individual light-emittingdistricts 15I˜15V, which are electrically connected with the wire bondareas 14I˜14V, respectively; such that a desired illumination pattern ofthe chip array structure 1 can thus be achieved. In the case that thecurrent to the wire bond area 14I is larger than that to any of theother wire bond areas 14II˜14V, any normal light-emitting element 12within the light-emitting district 15I would be brighter than thatwithin the light-emitting districts 15II˜15V, for the differences ininput currents. Upon such an arrangement, the light-emitting district15I will be the brightest one among the light-emitting districts 15I˜15Von the chip array structure 1, and thereby a Gaussian illuminationpattern can be achieved. On the other hand, in the case that the currentto the wire bond area 14I is smaller than that to any of the other wirebond areas 14II˜14V, any normal light-emitting element 12 within thelight-emitting district 15I would be darker than that within thelight-emitting districts 15II˜15V, again for the differences in inputcurrents. Upon such an arrangement, the light-emitting district 15I willbe the darkest one among the light-emitting districts 15I˜15V on thechip array structure 1, and thereby a donut-type illumination patterncan be achieved.

In the following descriptions upon other embodiments of the presentinvention, the same names and numbers will be given to those elementsthat are common in all embodiments including the foregoing firstembodiment. A tailing letter will be added to the number of any elementin the other embodiments that is similar to the element in the firstembodiment, though the same name would be still given at the same time.

Referring now to FIG. 3, a second embodiment of the chip array structurefor laser diodes in accordance with the present invention isschematically shown in a top view. The difference between the secondembodiment and the first embodiment is that the second embodimentincludes eight light-emitting districts 15 aI˜15 aVIII, and all theeight light-emitting districts 15 aI˜15 aVIII have the same amount ofthe light-emitting elements 12 though the geometrical configurationsthereof might be various. By compared to a formulation of having all thelight-emitting districts to have the same geometrical configuration, thesecond embodiment can take advantages of different shapes of thelight-emitting districts 15 aI˜15 aVIII so as to prevent from thedisadvantage donut-type illumination pattern resulted from strong photocoherence in laser resonance. In the second embodiment 1a of the chiparray structure as shown in FIG. 3, the eight light-emitting districts15 aI˜15 aVIII are defined by the insulation wall 13 a to separate thelight-emitting elements 12 a on the semiconductor chip 11 a, and each ofthe light-emitting districts 15 aI˜15 aVIII is electrically connected toa respective one of the isolated wire bond areas 14 aI˜14 aVIII througha corresponding connection electrode 16.

Accordingly, referred to FIG. 3, the light-emitting districts 15 aI˜15aVIII of the second embodiment of the chip array structure 1 a for laserdiodes in accordance with the present invention, separated by theinsulation wall 13 a, can be defined by ranges of correspondingcoordinates (x, y) in the X/Y coordinate system as follows.

Light-emitting district 15 aI: (2˜3, 3˜5), (4, 4˜5);

Light-emitting district 15 aII: (5˜6, 4˜6), (7, 4˜5);

Light-emitting district 15 aIII: (1˜4, 1), (1˜3, 2), (1, 3);

Light-emitting district 15 aIV: (1, 4˜8), (1, 6˜8);

Light-emitting district 15 aV: (3˜4, 6˜8), (5, 7˜8);

Light-emitting district 15 aVI: (6, 7˜8), (7˜8, 6˜8);

Light-emitting district 15 aVII: (7, 1˜3), (8, 1˜5); and

Light-emitting district 15 aVIII: (4, 2˜3), (5˜6, 1∥3).

As illustrated in FIG. 3, the light-emitting districts 15 aI and 15 aIIare surrounded by the other light-emitting districts 15 aIII˜15 aVIII.Also, the light-emitting districts 15 aI˜15 aVIII are individually, inan electric independence way, connected to the corresponding wire bondareas 14 aI˜14 aVIII whom are also electrically isolated from eachother. As shown, the locations of the wire bond areas 14 aI˜14 aVIIIwith respect to the array of the light-emitting elements 12 a aredefined as follows.

The wire bond area 14 aI for the light-emitting district 15 aI islocated lower at a left lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a;

The wire bond area 14 aII for the light-emitting district 15 aII islocated right at an upper lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a;

The wire bond area 14 aIII for the light-emitting district 15 aIII islocated left at a lower lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a;

The wire bond area 14 aIV for the light-emitting district 15 aIV islocated upper at the left lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a;

The wire bond area 14 aV for the light-emitting district 15 aV islocated left at the upper lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a;

The wire bond area 14 aVI for the light-emitting district 15 aVI islocated upper at a right lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a;

The wire bond area 14 aVII for the light-emitting district 15 aVII islocated lower at the right lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a; and

The wire bond area 14 aVIII for the light-emitting district 15 aVIII islocated right at the lower lateral side to (in FIG. 3) the array of thelight-emitting elements 12 a.

Referring now to FIG. 4, a third embodiment of the chip array structurefor laser diodes in accordance with the present invention isschematically shown in a top view. The difference between the thirdembodiment and the first embodiment is that the third embodimentincludes only four light-emitting districts 15 bI˜15 bIV, and each ofthe four light-emitting districts 15 bI˜15 bIV has a larger amount ofthe light-emitting elements 12 b than that in the first embodiment,though the geometrical configurations thereof are various. By comparedto a formulation of having all the light-emitting districts to have thesame geometrical configuration, the third embodiment can also takeadvantages of different shapes of the light-emitting districts 15 aI˜15aVIII to avoid the disadvantage donut-type illumination pattern resultedfrom strong photo coherence in laser resonance. In the third embodiment1b of the chip array structure as shown in FIG. 4, the fourlight-emitting districts 15 bI˜15 bIV are defined by the insulation wall13 b to separate the light-emitting elements 12 b on the semiconductorchip 11 b, and each of the light-emitting districts 15 bI˜15 bIV iselectrically connected to a respective one of the isolated wire bondareas 14 bI˜14 bIV through a corresponding connection electrode 16.

Accordingly, referred to FIG. 4, the light-emitting districts 15 bI˜15bIV of the third embodiment of the chip array structure 1 b for laserdiodes in accordance with the present invention, separated by theinsulation wall 13b, can be defined by ranges of correspondingcoordinates (x, y) in the X/Y coordinate system as follows.

Light-emitting district 15 bI: (3˜4, 4˜6), (5, 3˜6), (6, 3˜8);

Light-emitting district 15 bII: (1˜6, 1˜2), (1˜4, 3);

Light-emitting district 15 bIII: (1˜2, 4˜8), (3˜5, 7˜8); and

Light-emitting district 15 bIV: (7˜8, 1˜8).

As illustrated in FIG. 4, the light-emitting districts 15 bI is largelysurrounded by the other light-emitting districts 15 bII˜15 bIV. Also,the light-emitting districts 15 bI˜15 bIV are individually, in anelectric independence way, connected to the corresponding wire bondareas 14 bI˜14 bIV whom are also electrically isolated from each other.As shown, the locations of the wire bond areas 14 bI˜14 bIV with respectto the array of the light-emitting elements 12 b are defined as follows.

The wire bond area 14 bI for the light-emitting district 15 bI islocated left to (in FIG. 4) the array of the light-emitting elements 12b,

The wire bond area 14 bII for the light-emitting district 15 bII islocated lower to (in FIG. 4) the array of the light-emitting elements 12b;

The wire bond area 14 bIII for the light-emitting district 15 bIII islocated upper to (in FIG. 4) the array of the light-emitting elements 12b; and

The wire bond area 14 bIV for the light-emitting district 15 bIV islocated right to (in FIG. 4) the array of the light-emitting elements 12b.

Referring now to FIG. 5, a fourth embodiment of the chip array structurefor laser diodes in accordance with the present invention isschematically shown in a top view. The difference between the fourthembodiment and the first embodiment is that the fourth embodiment thoughincludes the same five light-emitting districts 15 cI˜15 cVI, but theamounts and the geometrical configurations of the light-emittingelements 12 c in the five light-emitting districts 15 cI˜15 cV aredifferent. By compared to a formulation of having all the light-emittingdistricts to have the same geometrical configuration, the fourthembodiment can be benefited from different shapes of the light-emittingdistricts 15 cI˜15 cV, by which the disadvantage donut-type illuminationpattern resulted from strong photo coherence in laser resonance can beavoided. In the fourth embodiment 1c of the chip array structure asshown in FIG. 5, the five light-emitting districts 15 cI˜15 cV aredefined by the insulation wall 13 c to separate the light-emittingelements 12 c on the semiconductor chip 11 c, and each of thelight-emitting districts 15 cI˜15 cV is electrically connected to arespective one of the isolated wire bond areas 14 cI˜14 cV through acorresponding connection electrode 16.

Accordingly, referred to FIG. 5, the light-emitting districts 15 cI˜15cV of the fourth embodiment of the chip array structure 1 c for laserdiodes in accordance with the present invention, separated by theinsulation wall 13 c, can be defined by ranges of correspondingcoordinates (x, y) in the X/Y coordinate system as follows.

Light-emitting district 15 cI: (2˜8, 1), (3˜8, 2), (4˜6, 3);

Light-emitting district 15 cII: (1, 1˜8), (2, 2˜7), (3, 3˜6);

Light-emitting district 15 cIII: (2˜5, 8), (3˜5, 7), (4˜5, 6);

Light-emitting district 15 cIV: (6˜8, 6˜8); and

Light-emitting district 15 cV: (4˜8, 4˜5), (7˜8, 3).

From the (x, y) definitions in FIG. 5, the light-emitting districts 15cIII and 15 cIV are located largely upper to the light-emittingdistricts 15 cII and 15 cV, and the light-emitting district 15 cI islocated largely lower to the light-emitting districts 15 cII and 15 cV.Also, each of the light-emitting districts 15 cI˜15 cV is electricallyand independently connected to a corresponding one of the isolated wirebond areas 14 cI˜14 cV via the respective connection electrodes 16. Asshown, the locations of the wire bond areas 14 cI˜14 cV with respect tothe array of the light-emitting elements 12 c are defined as follows.

The wire bond area 14 cI for the light-emitting district 15 cI islocated lower to (in FIG. 5) the array of the light-emitting elements 12c;

The wire bond area 14 cII for the light-emitting district 15 cII islocated left to (in FIG. 5) the array of the light-emitting elements 12c;

The wire bond area 14 cIII for the light-emitting district 15 cIII islocated left at a lateral side upper to (in FIG. 5) the array of thelight-emitting elements 12 c;

The wire bond area 14 cIV for the light-emitting district 15 cIV islocated right at the lateral side upper to (in FIG. 5) the array of thelight-emitting elements 12 c; and

The wire bond area 14 cV for the light-emitting district 15 cV islocated right to (in FIG. 5) the array of the light-emitting elements 12c.

Referring now to FIG. 6, a schematic top view of a preferred packagingdevice for the chip array structure for laser diodes in accordance withthe present invention is shown. As illustrated, the 8×8 array structure1 of the light-emitting elements 12 in the aforesaid first embodiment asshown in FIG. 2 is applied, for example, to the packaging device 10. Thepackaging device 10 provides a circuit board 2 to carry thereon the chiparray structure 1 for laser diodes.

In the present invention, the packaging device 10 includes the chiparray structure 1, the circuit board 2, a metal substrate 3, aconductive glue 4 and a plurality of metal wires 5. The chip arraystructure 1, as described above, is produced from a semiconductorprocess and includes a plurality of light-emitting elements 12, at leastone insulation wall 13, at least two wire bond areas 14, at least twolight-emitting districts 15 and a plurality of connection electrodes 16.The circuit board 2 for carrying thereon the metal substrate 3 cancouple electrically with a foreign printed circuit board (not shownherein) via leads 6, stems (not shown herein), pins (not shown herein)or terminals (not shown herein) provided under or lateral to the circuitboard 2. In the present invention, the circuit board 2 can be made of alow temperature co-fired ceramic (LTCC), a high temperature co-firedceramic (HTCC), a plastics, or any the like.

The metal substrate 3 engaged on the circuit board 2 has a supportsurface 31 to carry thereon the chip array structure 1 for laser diodesand the related metal wires 5. As shown in FIG. 6, the metal substrate 3further includes a first electrode area 32, at least a second electrodearea, and at least a third electrode area 35. The first electrode area32 contacted with the bottom surface 112 of the chip array structure 1has a surface area larger than the area of the bottom surface 112.Between the bottom surface 112 of the semiconductor chip 11 and thefirst electrode area 32, the conductive glue 4 is provided to establishthe electric coupling as well as the satisfactory adhering in between.In particular, the whole metal substrate 3 can thus perform the N-poleground due to the contact of the first electrode area 32 and the bottomsurface 112 of the semiconductor chip 11. On the other hand, the secondelectrode area 33 is to perform the respective P-pole electrode isolatedto the first electrode area 32. In the present invention, the conductiveglue 4 is preferable to be a solder paste, which is featured inexcellent thermo-conductivity for bridging the chip array structure 1and the first electrode area 32. By compared to the conventional silverpaste, the adhering provided by the solder paste can present better heatconduction and dissipation.

In the present invention, the metal substrate 3 is made of a copper,aluminum, gold, copper alloy, aluminum alloy, or any metal or alloy thelike. Also, the first electrode area 32, the second electrode area 33and the third electrode area 35 on the metal substrate 3 can be madefrom plating, printing, or depositing of a silver, copper, gold, or anymetal or alloy the like, so as to enhance the electric conductivity ofconcerned areas and the adhesion in between with the wiring. In thepresent invention, the metal substrate 3 made of the copper, aluminum,gold, or alloy of the foregoing metals can present better heatconduction and dissipation than the conventional Ni—Fe alloy substrate.The first electrode area 32 and the second electrode areas 33 areelectrically separated by an insulation structure 34. Similarly, thefirst electrode area 32 and the third electrode areas 35 are alsoelectrically separated by the same insulation structure 34. In thepresent invention, the second electrode areas 33 and the third electrodeareas 35 are independent electrode areas distributed largely around thechip array structure 1, mainly at the upper and the lower sides thereof.The insulation structure 34 can be made of an insulation paint, ceramic,or any insulation material the like.

As shown in FIG. 6, the packaging device 10 for the chip array structure1 in accordance with the present invention includes five secondelectrode areas 33 (P electrode) located respectively at the upper leftcorner, the left-hand side of the upper side, the right-hand side of theupper side, the upper right corner and the lower side with respect tothe chip array structure 1, in which the second electrode areas 33 atthe upper left and right corners are formed as L shapes to shield therespective corners of the chip array structure 1. Each of the secondelectrode areas 33 is electrically coupled with the corresponding wirebond area 14 of the chip array structure 1 via the respective metalwires 5 structured by a wire-bonding process. In addition, two of thethird electrode areas 35 (N electrode) also formed as corresponding Lshapes are located to the lower left and right corners of the chip arraystructure 1, for accounting to the second electrode areas 33 (Pelectrode) at the upper left and right corners as described above. Thethird electrode areas 35 and the first electrode area 32 areelectrically coupled by the respective metal wires 5 in a previouswire-bonding process.

As shown in FIG. 6, the metal wires 5 are produced from a wire-bodingprocess to bridge the individual wire bond areas 14 and thecorresponding second electrode areas 33, and to bridge the firstelectrode area 32 and the individual third electrode areas 35.Preferably, the metal wires 5 are made of gold. In the presentinvention, by providing a wire-bonding process, the metal wires 5 canextend between the wire bond areas 14 of the chip array structure 1 andthe second electrode areas 33 at the aforesaid five positions so as toestablish electric connections in between. In this wire-bonding process,no matter how many the metal wires 5 are, the metal wires 5 are notcrossed each other, not across over the array of the light-emittingelements 12, and thus not to shade the lights from the light-emittingelements 12.

In the present invention, the packaging device 10 for the chip arraystructure 1 further includes a plurality of leads 6 extended from thecircuit board 2 and electrically coupled with the respective secondelectrode areas 33 (P electrode), or either the respective thirdelectrode areas 35 (N electrode) or the first electrode area 32 (Nelectrode), through the circuit board 2. By providing the leads 6, thepackaging device 10 for the chip array structure 1 of the presentinvention can be then applied to a surface mount device (SMD). Further,for a broader surface area is defined to the second electrode area 33and also for the plurality of the wire bond areas 14 are electricallyindependent, heat generated by the array of the light-emitting elements12 can be effectively dissipated. By providing different currents to thewire bond areas 14, various illumination patterns can be achieved.Further, for the packaging device 10 for the chip array structure 1 ofthe present invention can allow more metal wires 5 to transmit powersignals, design easiness and flexibility in current distribution,resistance reduction and circuit layout can be obtained. Moreover, lessheat generation is also one of many merits of the present invention.

While the present invention has been particularly shown and describedwith reference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may bewithout departing from the spirit and scope of the present invention.

What is claimed is:
 1. A chip array structure for laser diodes, formedon an active surface of a semiconductor chip produced by a semiconductorprocess, comprising: a plurality of light-emitting elements in an arrayarrangement; at least one insulation wall for separating the pluralityof light-emitting elements into at least two light-emitting districts;at least two wire bond areas, located at positions respective to the atleast two light-emitting districts; and a plurality of connectionelectrodes individually for electrically connecting the at least twowire bond areas to the respective at least two light-emitting districts;wherein each of the at least two light-emitting districts iselectrically independent, the semiconductor chip has a bottom surfaceincluding thereon an electrode layer having a polarity different to thatof the at least two wire bond areas, and the at least two wire bondareas have individual but identical polarity.
 2. The chip arraystructure for laser diodes according claim 1, wherein said plurality oflight-emitting elements are selected from a group of vertical cavitysurface emitting Lasers (VCSEL), horizontal cavity surface emittingLasers (HCSEL), and resonant cavity light emitting diodes (RCLED). 3.The chip array structure for laser diodes according claim 1, whereinsaid at least two light-emitting districts have individual geometricalconfigurations.
 4. The chip array structure for laser diodes accordingclaim 1, wherein each of said at least two light-emitting districtsincludes an individual amount of said light-emitting elements and anindividual current input so as to control brightness of saidlight-emitting district.
 5. A packaging device for a chip arraystructure for laser diodes, comprising: a metal substrate, having asupport surface to carry thereon a first electrode area, at least onesecond electrode area and at least one third electrode area; aninsulation structure for electrically separating the first electrodearea, each of the at least one second electrode area and each of the atleast one third electrode area; a semiconductor chip, produced by asemiconductor process, having thereof an active surface to includethereon a plurality of light-emitting elements in an array arrangement,at least one insulation wall for separating the plurality oflight-emitting elements into at least two light-emitting districts, atleast two wire bond areas located at positions respective to the atleast two light-emitting districts, and a plurality of connectionelectrodes individually for electrically connecting the at least twowire bond areas to the respective at least two light-emitting districts;a conductive glue, located, thus for establishing electric connection,between a bottom surface of the semiconductor chip and the firstelectrode area a plurality of metal wires, and a plurality of connectionelectrodes individually for electrically connecting the at least twowire bond areas to the respective at least two light-emitting districts;wherein each of the at least two light-emitting districts iselectrically independent, a polarity of the bottom surface is differentto that of the at least two wire bond areas, and the at least two wirebond areas have individual but identical polarity.
 6. The packagingdevice for a chip array structure for laser diodes according to claim 5,wherein said metal substrate is made of a material selected from a groupof copper, aluminum, gold, and related alloys, and said plurality oflight-emitting elements are selected from a group of vertical cavitysurface emitting Lasers (VCSEL), horizontal cavity surface emittingLasers (HCSEL), and resonant cavity light emitting diodes (RCLED). 7.The packaging device for a chip array structure for laser diodesaccording to claim 5, wherein said at least two light-emitting districtshave individual geometrical configurations.
 8. The packaging device fora chip array structure for laser diodes according to claim 5, whereineach of said at least two light-emitting districts includes anindividual amount of said light-emitting elements and an individualcurrent input so as to control brightness of said light-emittingdistrict.
 9. The packaging device for a chip array structure for laserdiodes according to claim 5, further including a circuit board engagedthereon said metal substrate, the circuit board being made of a materialselected from a group of a low temperature co-fired ceramic (LTCC), ahigh temperature co-fired ceramic (HTCC) and a plastics.
 10. Thepackaging device for a chip array structure for laser diodes accordingto claim 9, further including a plurality of leads extended from saidcircuit board and electrically coupled with said at least one secondelectrode area, or either said at least one third electrode area or saidfirst electrode area.